Timing Driven Placement Recon guration for Fault Tolerance and Yield Enhancement in FPGAs

The architectural regularity of FPGAs provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of recon guring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement recon guration is to minimize timing degradation. The concept of a slack neighborhood graph is used as a general tool for timing driven recon guration with a low increase in critical path delay. Our algorithm simultaneously achieves both provably low timing degradation and low re-programming cost. For a wide range of fault probabilities and circuits our algorithm successfully recon gures the placement with less than 1% degradation in the circuit delay.